Semiconductor memory device
US7467337B2 · kind B2 · utility
21Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Mar 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.