Methods and apparatus for compiler managed first cache bypassing
US7467377B2 · kind B2 · utility
20Cited by
27References
54Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2002 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jun 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.