Method and resulting structure for fabricating test key structures in DRAM structures
US7468283B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2007 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Mar 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.