Packaging of hybrid integrated circuits
US7468556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2007 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Jun 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Improved sensor packaging is provided with a hybrid integration approach. In one example, an application specific integrated circuit (ASIC) for sensor signal conditioning is packaged. The ASIC package has an aperture in it that exposes a chip to chip bonding interface of the ASIC chip. The rest of the ASIC chip is surrounded by the package, including the connections between the external package leads and the ASIC chip. A sensor chip, also having a chip to chip bonding interface, is disposed in the package aperture and bonded to the ASIC chip such that the two chip to chip bonding interfaces are connected. Flip chip bonding of the sensor chip to the ASIC chip is a preferred approach for chip to chip bonding. The vertical gap between the two chips can be filled in by an underfill process. The lateral gap between the sensor chip and the package can also be filled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.