Apparatus and related method for level clamping control
US7468760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/52
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.