Canceller circuit and controlling method
US7468957B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A canceller circuit includes a subtractor, receiving an analog received signal and a replica signal of noise (e.g., echo and/or crosstalk), for carrying out subtraction on the received signal and the replica signal in a continuous time analog domain, an analog-to-digital converter for converting an analog signal output from the subtractor to a digital signal, an adaptive filter, receiving a noise reference signal and an output signal of the analog-to-digital converter, for outputting the replica signal of noise, as a digital signal, a digital-to-analog converter for receiving and converting a digital signal output from the adaptive filter, to an analog signal, and for supplying the analog signal to the subtractor as the replica signal of noise, and a control circuit for variably controlling the sampling phase in the digital-to-analog converter independently of the sampling phase on the side of the analog-to-digital converter, the phase of the signal waveform of the replica signal of the noise, output from the digital-to-analog converter, being controlled by the control circuit to be coincident with the phase of noise received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.