System independent and scalable packet buffer management architecture for network processors
US7468985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Jul 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/901
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.