Methods and devices for synchronizing the timing of logic cards in a packet switching system without data loss
US7468991B2 · kind B2 · utility
1Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2003 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Feb 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.