Method for using partitioned masks to build a chip

US7469401B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Subhrajit Bhattacharya · White Plains, US
• John Darringer · Mahopac, US
• Daniel L. Ostapko · Mahopac, US

Key dates

• Filing date: Feb 22, 2006
• Grant date: Dec 23, 2008
• Expiry date: Jul 19, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.