Method of manufacturing a thin film transistor
US7470579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0321
Abstract
A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of the channel region, and offset regions, each offset regions disposed between the channel region and one of the source and drain regions at both sides of the channel region, a gate insulating layer covering the channel region and the offset regions disposed at both sides of the channel region excluding the source and drain regions, and a gate layer formed on the channel region excluding the offset regions. The thin film transistor has the structure in which an offset or LDD is obtained without an additional mask process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.