Approach to reduce parasitic capacitance from dummy fill
US7470630B1 · kind B1 · utility
9Cited by
16References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Nov 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than the interconnect metal lines. To form this structure, first and second pluralities of trenches are formed in the dielectric layer. At least one of the second plurality of trenches is shallower than the first plurality of trenches. The first and second pluralities of trenches are filled with a conductive layer and then planarized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.