Barrier layer stack to prevent Ti diffusion
US7470992B2 · kind B2 · utility
3Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jul 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A barrier layer stack. The barrier layer stack includes a semiconductor process wafer comprising an exposed conductive region, a first barrier layer stack comprising at least one TiN and one Ti layers overlying and contacting the conductive region, wherein the TiN layer is contacted with the Ti layer, and an overlying aluminum alloy layer in contact with the first barrier layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.