Slew-rate controlled pad driver in digital CMOS process using parasitic device cap
US7471111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Apr 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.