Delay locked loop with common counter and method thereof
US7471131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Aug 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.