Optimized circuits for three dimensional packaging and methods of manufacture therefore
US7471146B2 · kind B2 · utility
1Cited by
33References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Dec 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09972
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.