Signal degradation monitoring
US7471161B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jun 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/159
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Provided are a method, system, and device to monitor degradation of a signal due to circuit aging. In one embodiment, a signal may be applied to a data path prior to aging of the circuit producing the signal to provide a reference value. The signal generating circuit may then be aged while the data path is disabled to protect the data path from the effects of circuit aging. Upon reenabling the data path, the signal may be reapplied in an after stress test to measure the effects of circuit aging on the circuitry generating the signal. For example, the effects of circuit aging may be measured for clock duty cycle degradation, clock skew degradation and signal margin degradation as well as other signal parameters. Additional embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.