Analog-to-digital converter with low latency output path
US7471229B2 · kind B2 · utility
3Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2007 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Apr 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.