Semiconductor memory devices, block select decoding circuits and method thereof
US7471589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.