Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
US7472038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Apr 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.