Mirrored memory
US7472221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2004 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jan 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.