Multi-cycle instructions
US7472259B2 · kind B2 · utility
0Cited by
17References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.