Double data rate system
US7472304B2 · kind B2 · utility
12Cited by
8References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.