Method and apparatus for limiting the output frequency of an on-chip clock generator
US7472305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Mar 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the reference clock input signal frequency with minimum and maximum calibration word signals, in order to determine if the reference clock input signal frequency is within a permitted range. If the reference clock input signal frequency is not within the permitted range, the apparatus sends a tamper alert to the chip or to a system, and the output clock signal frequency is not changed according to the reference clock input signal frequency, thereby protecting the chip from erroneous or tampered clock signal. The output clock signal is buffered from the reference clock input signal insuring that the output clock signal frequency is within the permitted range. The apparatus can operate without providing the reference input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.