Processor timing apparatus, systems, and methods
US7472306B2 · kind B2 · utility
21Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption. The status indicators may indicate the status of routers coupled to the processors. Additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.