Mechanism to stop instruction execution at a microprocessor
US7472323B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.