Method for improved single event latch up resistance in an integrated circuit
US7474011B2 · kind B2 · utility
5Cited by
0References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/929
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.