Bias device clamping circuit for fast over-range recovery
US7474154B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45641
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gain-boosted telescopic amplifier (100) includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (MP1, MN1), a pair of NMOS gain-boosted cascode transistors (MP2, MN2) and a pair of PMOS gain-boosted cascode transistors (MP3, MN3). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.