Frequency calibration for frequency synthesizers
US7474159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A calibration circuit (17) for calibrating a frequency synthesizer (10) having a voltage-controlled oscillator (VCO) (15) with a plurality of switched-capacitor arrays (CA1-CAn). The calibration circuit (17) counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer (10) than would be possible using the reference-clock signal (ref_clk). The calibration circuit (17) compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.