Shift register latch with embedded dynamic random access memory scan only cell
US7474574B1 · kind B1 · utility
3Cited by
3References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 2, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jul 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.