Frame alteration logic for network processors
US7474672B2 · kind B2 · utility
5Cited by
19References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Dec 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.