Variable load circuit for reducing quadrature phase error
US7474715B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jun 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable load circuit for adjusting a phase of a differential signal including a first transistor having a first terminal adapted to receive a first component of the differential signal, a second transistor having a first terminal adapted to receive a second component of the differential signal and a second terminal coupled to a second terminal of the first transistor, and a variable current source coupled to a third terminal of both the first and second transistors. The variable current source generates a bias current based on a control signal. For each of the first and second transistors, a first capacitance is created between the first and second terminals, and a second capacitance is created between the first and third terminals. The first and second capacitances are each a function of the bias current and thus the control signal and operate to adjust the phase of the differential signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.