Systems and methods for sample rate conversion using multiple rate estimate counters
US7474722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jun 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for using multiple rate estimate counters in converting input data streams having variable sample rates to an output sample rate that are used in processing the data streams. In one embodiment, a system includes a clock source, first and second counters coupled to the clock source and configured to count cycles for corresponding data streams, and a data processor coupled to the first and second counters. The data processor is configured to read the number of cycles counted by each of the counters between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted, and to convert the second data stream to the predetermined output sample rate based on the ratio of the numbers of cycles counted in the first and second counters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.