Multi-processor module
US7475175B2 · kind B2 · utility
13Cited by
16References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2004 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Nov 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.