System-on-a-chip mixed bus architecture
US7475182B2 · kind B2 · utility
13Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2005 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.