Hybrid parallel/serial bus interface
US7475273B2 · kind B2 · utility
8Cited by
35References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.