Scan test method, integrated circuit, and scan test circuit
US7475306B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Mar 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan test method of an integrated circuit including a combinational circuit and flip-flops forming a scan chain is disclosed. The method first sets an initial test value to the flip-flops forming the scan chain by serial scan input. Then, it repeats a capture operation and a feedback shift operation. The capture operation captures an output of the combinational circuit, to which a value set to a flip-flop has been applied, by another flip-flop. The feedback shift operation feeds an output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain. Finally, it compares an output of the scan chain with an expected value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.