Error detection and correction method and system for memory devices
US7475326B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2004 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jan 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for the detection and correction of errors in memory systems is disclosed. In one embodiment, a method of error detection in a memory system having a plurality (m>1) of memory devices includes generating check bits for each of a plurality of data sets, dividing each memory device into a plurality (n>1) of segments. The plurality of data sets are interleaved to form a plurality (p>1) of words. Each word includes at least one segment from two or more of the memory devices. Detection and correction may utilize oneor more parallel Reed-Solomon decoder and encoder. The system and method allow for the efficient detection and/or correction of memory device errors and bit errors in one or more memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.