Method and system for performing non-local geometric operations for the layout design of a semiconductor device
US7475376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an automatic check is performed to determine if the output of a parent region is compatible with the output of a current region of a cell. If the output of the parent region is compatible with the output of the current region of a cell, the output of the parent region is reduced (e.g., an ANDNOT operation) taking into account the current region. If the output of the parent region is not compatible with the output of the current region of a cell, the incompatible output of the sub-region is copied to a promote container and the incompatible output is promoted to the output of all other parent regions. These steps are performed for all parent regions. The layout hierarchy is first generated from the input data, and then is also generated from the region data. The difference between the layout hierarchy generated from the input data and the layout hierarchy generated from the region data is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.