Patent · US Active

Shallow trench avoidance in integrated circuits

US7475381B2 · kind B2 · utility

1Cited by
0References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 30, 2006
Grant dateJan 6, 2009
Priority date—
Expiry dateMay 9, 2027

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02P90/02
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.