Electronic and optoelectronic component packaging technique
US7476566B2 · kind B2 · utility
5Cited by
47References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging method including assembling components on a substrate, manufacturing a lid assembly to include a plurality of integrated covers, and mating the lid assembly to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.