Multilayer flip-chip substrate interconnect layout
US7476813B2 · kind B2 · utility
2Cited by
9References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2003 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Aug 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The multilayer substrate includes a plurality of layers. Located within the plurality of layers are a number of vias. Conductive traces connect the vias to form trace/via paths having various topologies, geometries, and/or properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.