Rapid interconnect and logic testing of FPGA device
US7477070B2 · kind B2 · utility
2Cited by
3References
22Claims
0Family size
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Key dates
| Filing date | Dec 5, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Aug 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.