Power-optimized analog-to-digital converter (ADC) input circuit
US7477178B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2007 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jun 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/494
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise performance level. The selection of the combination of enabled amplifiers may be made in conformity with the sample rate of the converter and the amplifiers may have evenly-weighted bias currents, or unevenly weighed bias currents and may be optimized for their particular use in combinations for bandwidth and 1/f noise corner performance. The outputs of the amplifiers are combined in a combiner circuit, which may be a discrete-time chopping amplifier that receives charges from a plurality of capacitors that sample each enabled amplifier output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.