Dynamic random access memory device and associated refresh cycle
US7477563B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Dec 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory device having reduced power consumption and a refresh cycle method. The memory device includes a monitoring address storage unit storing multiple monitoring addresses, an error correction code (ECC) engine detecting whether or not an error occurs in monitoring bits corresponding to the monitoring addresses, and a refresh cycle determining circuit adjusting a self refresh cycle depending on whether or not an error occurs in the monitoring bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.