Microarchitectural wire management for performance and power in partitioned architectures
US7478190B2 · kind B2 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Feb 10, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.