Duplex system
US7478274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | May 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A duplex system has duplicated processor devices. Each of the processor devices has a first copying section which writes data written in a memory of the processor device, into a same address of a memory of the other processor device, a second copying section which divides all data in the memory of the processor device to sequentially write all data into the memory of the other processor device periodically, an error detecting section which checks the data written in the memory of the processor device, and an error check register which sets an error bit when the error detecting section detects an error. After the first copying section and the second copying section write data into a memory of the standby side processor device, the control side processor device checks an error bit of an error check register of the standby side processor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.