Circuit and method of detecting and resolving stuck I2C buses
US7478286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jan 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A integrated circuit (IC) implementation of a protection circuit detects and resolves a fault on a bus, such as a stuck-low condition on an I2C bus. The circuit includes logic that detects a fault condition caused by the slave device, e.g. when one or both lines are low for a period longer than a timeout value in the I2C example. Upon detecting the fault condition, the logic disconnects the slave device from the data line and the clock line, for example by activation of switches incorporated in the IC. This typically frees the bus for use by other devices. The logic may also send the slave device one or more clock signals to clear the fault and/or a stop bit when the fault clears to reset the data register in the slave device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.