Processor fault isolation
US7478299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jul 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods, apparatus, and products for processor fault isolation are disclosed that include sending, by an embedded system microcontroller to a programmable logic device (‘PLD’) a selection signal identifying one processor for boundary scan operations; sending boundary scan input signals to be sent to the identified processor; multiplexing by the PLD the boundary scan input signals to the identified processor; and sending boundary scan output signals returned from the identified processor. Methods, apparatus, and products for processor fault isolation are also disclosed that include connecting two or more processors in a boundary scan test chain, the connecting carried out by a PLD of a computer, the PLD further connected to sense lines carrying presence signals indicating whether processors are present in the computer; and including in the chain all processors indicated present according to presence signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.