Method of detecting error location, and error detection circuit, error correction circuit, and reproducing apparatus using the method
US7478306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jul 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/1272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error correction circuit capable of detecting burst errors included in a data signal with reliability. The error correction circuit comprises a reading unit, a first estimation unit, a second estimation unit, and a correction unit. The reading unit reads the data signal. The first estimation unit estimates error locations based on BIS code included in the data signal, and stores the locations into an error location storing unit. The second estimation unit estimates error locations based on characteristics of bit strings adjoining the BIS code, and stores the locations into the error location storing unit. The correction unit identifies erasure locations based on the error locations stored in the error location storing unit, and performs erasure correction on the erasure locations identified. Since the error locations are estimated based on the BIS code and the characteristics of the bit strings adjoining the BIS code as well, it is possible to detect burst errors without fail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.