Method for fabricating an integrated circuit comprising a three-dimensional capacitor
US7479424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2006 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Jan 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.